📄 Paper Accepted at DIMES '25

A paper first-authored by Luhao Liu, an undergraduate student in the Shinagawa Laboratory, has been accepted at the 3rd Workshop on Disruptive Memory Systems.

This paper proposes Shinano, which extends the FPGA shell [Coyote v2 (SOSP 2025)] by enabling dynamic switching between FPGA-side TLB configurations, thereby improving application performance for different workloads.

To optimize sequential virtual address accesses common in streaming applications, we introduce two techniques: Stream TLB, which maps multiple contiguous pages into a single TLB entry, and Dynamic TLB, which allows runtime changes of page size via a global register. These techniques achieve up to 4× higher memory coverage compared to prior systems with equivalent hardware resources.

This research is a collaboration with the group of Prof. Gustavo Alonso at ETH Zurich, where Liu studied abroad.