<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Formal Verification | Shinagawa Laboratory</title><link>https://www.os.is.s.u-tokyo.ac.jp/en/category/formal-verification/</link><atom:link href="https://www.os.is.s.u-tokyo.ac.jp/en/category/formal-verification/index.xml" rel="self" type="application/rss+xml"/><description>Formal Verification</description><generator>Hugo Blox Builder (https://hugoblox.com)</generator><language>en-us</language><lastBuildDate>Tue, 08 Jul 2025 00:00:00 +0000</lastBuildDate><image><url>https://www.os.is.s.u-tokyo.ac.jp/media/icon_hu3991700760012411192.png</url><title>Formal Verification</title><link>https://www.os.is.s.u-tokyo.ac.jp/en/category/formal-verification/</link></image><item><title>vRM: Verifying Reference Monitors via Exhaustive Access Pattern Generation</title><link>https://www.os.is.s.u-tokyo.ac.jp/en/publication/conference/2025-compsac-nakashima/</link><pubDate>Tue, 08 Jul 2025 00:00:00 +0000</pubDate><guid>https://www.os.is.s.u-tokyo.ac.jp/en/publication/conference/2025-compsac-nakashima/</guid><description/></item></channel></rss>